1. Field of the Invention
This invention relates to an improved electronic computer, and more particularly to an electronic computer capable of executing a plurality of instructions simultaneously and to an electronic computer capable of supporting a plurality of bus protocols.
2. Description of the Related Art
RISC processors capable of executing instructions at high speeds have been used for parallel arithmetic operation that deals with a plurality of instructions at the same time. Recently, much faster super-scalar processors have been developed; one of commercialized models of this type is Intel's 80960CA.
RISC processors are rich in software resources available. In developing super-scalar processors, to make full use of the existing software, it is necessary to develop processors that have object compatibility with the existing software.
Some of RISC processors use delayed branching or squashed branching techniques in order to reduce losses due to wasteful actions in executing branch instructions. Typical processors of this type are Sun Microsystems' R2000 and R3000. In delayed branching, when a branch instruction is encountered, the instruction immediately after the branch instruction is executed and then the branch destination instruction is executed. In squash branching, when a branch instruction is encountered, in the case of a branch-not-taken mode, the instruction next to the branch instruction is not executed, but the next instruction is executed, while in the case of a branch-taken mode, the instruction next to the branch instruction is executed and then the branch destination instruction is executed.
Because super-scalar processors are fast in executing instructions but complex in control, it is difficult to directly execute the object codes of RISC machines using the above-described delayed branching or squash branching technique. As a consequence, super-scalar processors have no object compatibility with programs for RISC processors that perform delayed branch instructions or squash branch instructions.
For example, the Intel super-scalar processor 80960CA has object compatibility with the Intel's RISC processor 80960KA. However, at present, the 80960KA has not used delayed branching or squash branching techniques.
As noted above, super-scalar processors, which have recently been developed in place of RISC processors, cannot execute delayed branch or squash branch instructions as matters stand. Therefore, they have no object compatibility with programs for RISC processors capable of executing those types of branch instructions.
In a multiprocessor system having a plurality of processors, there is a time when communication between processors coexists with data communication between a processor and other peripheral units. In this case, the protocol of data transfer procedure for each communication is different from the other. Thus, to achieve those two types of communication, it is necessary to actively switch bus protocols depending on the communication mode used.
However, for a system where processor-to-processor communication and processor-to-peripheral communication coexist, an effective means has not yet been found which switches bus protocols according to mode to allow those two types of communications on the same system.
Some electronic computers employ a copy-back virtual cache system. In such computers, such as the SUN workstation, the cache tag of the cache memory is provided with a dirty bit and the TLB (address translation buffer) is assigned a dirty page bit. Those computers have a hardware mechanism that asserts the dirty bit of the cache tag when data is stored in the cache memory, and that copies into the TLB dirty page bit the dirty bit of the cache line to be copied back when copy back occurs, which action indicates that data has been written into the page. By the above operation, the hardware mechanism rewrites the TLB dirty page bit at the time of uncached write access.
However, computers with a virtual cache system rewrite the TLB dirty page bit by means of hardware, which results in more complicated hardware construction, larger LSI chip size, and longer development time.
Among related literature are "IBM RISC System 1600 Technology," 1990, IBM Corporation, and "80960 Users' Manual," Intel Corporation.